(Hong Kong)
Product Summary
The EP1C20F324C8N contains a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between LABs and embedded memory blocks.
Parametrics
EP1C20F324C8N absolute maximum ratings: (1)VCCINT, Supply voltage, With respect to ground: –0.5 to 2.4V; (2)VCCIO: –0.5 to 4.6 V; (3)VCCA, Supply voltage, With respect to ground: –0.5 to 2.4V; (4)VI, DC input voltage: –0.5 to 4.6V; (5)IOUT, DC output current, per pin: –25 to 25 mA; (6)TSTG, Storage temperature, No bias: –65 to 150 ℃; (7)TAMB, Ambient temperature, Under bias: –65 to 135 ℃; (8)TJ, Junction temperature, BGA packages under bias: 135℃.
Features
EP1C20F324C8N features: (1)Up to 294,912 RAM bits (36,864 bytes); (2)Supports configuration through low-cost serial configuration device; (3)Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards; (4)Support for 66- and 33-MHz, 64- and 32-bit PCI standard; (5)High-speed (640 Mbps) LVDS I/O support; (6)Low-speed (311 Mbps) LVDS I/O support; (7)311-Mbps RSDS I/O support; (8)Up to two PLLs per device provide clock multiplication and phase shifting; (9)Up to eight global clock lines with six clock resources available per logic array block (LAB) row; (10)Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM; (11)Support for multiple intellectual property (IP) cores, including; (12)Altera MegaCore functions and Altera Megafunctions Partners; (13)Program megafunctions.
Diagrams
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 EP1C20F324C8N |
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IC CYCLONE FPGA 20K LE 324-FBGA |
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